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[세미나] SRAM-based In-Memory Computing Hardware for Energy-Efficient AI: Analog and Digital Approaches
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[세미나] SRAM-based In-Memory Computing Hardware for Energy-Efficient AI: Analog and Digital Approaches

O Speaker: Prof.Mingoo Seok (Columbia Univ.) O Title: SRAM-based In-Memory Computing Hardware for Energy-Efficient AI: Analog and Digital Approaches O Date: 22.08.19(fri.)  O Start Time: 11:00AM O Venue: E3-2#2201(우리별세미나실) OAbstract: In the last decade, SRAM-based in-memory computing (IMC) hardware has received significant research attention for its massive energy efficiency and performance boost. This seminar will […]

2022-08-10

O Speaker: Prof.Mingoo Seok (Columbia Univ.)

O Title: SRAM-based In-Memory Computing Hardware for Energy-Efficient AI: Analog and Digital Approaches

O Date: 22.08.19(fri.) 

O Start Time: 11:00AM

O Venue: E3-2#2201(우리별세미나실)

OAbstract:

In the last decade, SRAM-based in-memory computing (IMC) hardware has received significant research attention for its massive energy efficiency and performance boost. This seminar will introduce two very recent hardware prototypes, MBIMC (CICC’22) and DIMC (ISSCC’22), which achieve state-of-the-art performance and energy efficiency, yet leverage very different computing mechanisms. Specifically, MBIMC adopted analog-mixed-signal (AMC) computing mechanisms (capacitive coupling and charge sharing), achieving 177 TOPS/W for 4-bit weight and 4-b activation deep convolution neural networks (DCNN). On the other hand, DIMC adopted a fully digital approach, achieving 248 TOPS/W for 1-bit weight and 4-b activation DCNNs. After introducing each prototype in detail, we will compare the AMS and digital approaches for SRAM-based IMC hardware.

O Bio:

Mingoo Seok is an associate professor of Electrical Engineering at Columbia University. He received his B.S. from Seoul National University, South Korea, in 2005, and his M.S. and Ph.D. degree from the University of Michigan in 2007 and 2011, respectively, all in electrical engineering. His research interests are various aspects of VLSI circuits and architecture, including ultra-low-power integrated systems, cognitive and machine-learning computing, an adaptive technique for the process, voltage, temperature variations, transistor wear-out, integrated power management circuits, event-driven controls, and hybrid continuous and discrete computing. He won the 2015 NSF CAREER award and the 2019 Qualcomm Faculty Award. He is the technical program committee member for multiple conferences, including IEEE International Solid-State Circuits Conference (ISSCC). In addition, he has been an associate editor for IEEE Transactions on Circuits and Systems Part I (TCAS-I) (2014-2016), IEEE Transactions on VLSI Systems (TVLSI) (2015-present), IEEE Solid-State Circuits Letter (SSCL) (2017-present), and as a guest associate editor for IEEE Journal of Solid-State Circuits (JSSC) (2019).

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